10 Gbit/s bit interleaving CDR for low-power PON

نویسندگان
چکیده

برای دانلود باید عضویت طلایی داشته باشید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

‏‎design of an analog ram (aram)chip with 10-bit resolution and low-power for signal processing in 0/5m cmos process‎‏

برای پردازش سیگنال آنالوگ در شبکه های عصبی ، معمولا نیاز به یک واحد حافظه آنالوگ احساس میشود که بدون احتیاج به ‏‎a/d‎‏ و‏‎d/a‎‏ بتواند بطور قابل انعطاف و مطمئن اطلاعات آنالوگ را در خود ذخیره کند. این واحد حافظه باید دارای دقت کافی ، سرعت بالا ، توان تلفاتی کم و سایز کوچک باشد و همچنین اطلاعات را برای زمان کافی در خود نگهدارد. برای پیاده سازی سیستمی که همه این قابلیتها را در خود داشته باشد، کوشش...

15 صفحه اول

Adaptive Power Saving Mechanism for 10 Gigabit Class PON Systems

This paper proposes a power saving mechanism with variable sleep period to reduce the power consumed by optical network units (ONUs) in passive optical network (PON) systems. In the PON systems based on time division multiplexing (TDM), sleep and periodic wake-up (SPW) control is an effective ONU power saving technique. However, the effectiveness of SPW control is fully realized only if the sle...

متن کامل

A Low-Power, Small-Size 10-Bit Successive-Approximation ADC

A new Successive-Approximation ADC (Analog-toDigital Converter) was designed which not only consumes little power, but also requires a small chip area. To achieve those goals, both comparator and internal DAC (Digital-to-Analog Converter) have been improved. The ADC was designed in a 1.2 μm CMOS double-poly double-metal n-well process. It performs 10-bit conversion with 67 dB SFDR. Power consum...

متن کامل

Modified 32-Bit Shift-Add Multiplier Design for Low Power Application

Multiplication is a basic operation in any signal processing application. Multiplication is the most important one among the four arithmetic operations like addition, subtraction, and division. Multipliers are usually hardware intensive, and the main parameters of concern are high speed, low cost, and less VLSI area. The propagation time and power consumption in the multiplier are always high. ...

متن کامل

Adaptive Interleaving for Bit-Interleaved Coded Modulation

In this paper interleaver design for bit-interleaved coded modulation and systems with channel-state information at the transmitter is investigated. Based on the bit level capacities of an equivalent channel model an advantageous interleaver design is proposed. Understanding the varying level capacities as the result of a “fading” process, suited bit metric arrangements in the decoder can signi...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

ژورنال

عنوان ژورنال: Electronics Letters

سال: 2012

ISSN: 0013-5194

DOI: 10.1049/el.2012.3200